A HARDWARE IMPLEMENTATION OF A RISC-V PROCESSOR WITH PIPELINE PROCESSING THAT SUPPORTS THE RV32IM INSTRUCTION SET

Abstract

This paper briefly describes an implementation of the RV32IM instruction set that supports five stages of pipeline processing with hazard detection. The usual pipeline stages were used: IF, ID, EXE, MEM and WB. The starting point of the work was the initial version of the RV32I processor. The implementation of the complete I set of instructions followed. After that, the M instruction set was added. For implementation of the M instruction set, two ways of approaching the realization are taken into account. Both approaches produce the same logical results, the difference being in performance. The first method uses the Booth-4 algorithm, and the second uses DSPs from the Zybo board for multiplication instructions. The paper ends with a comparison of the performance of the RV32I processor with the RV32IM (Booth-4 algorithm and DSP).