IMPLEMENTATION OF CACHE SUBSYSTEM FOR RISC-V PROCESSOR
DOI:
https://doi.org/10.24867/10BE44MiseljicKeywords:
Cache memory, RISC-V, FPGA, ZyboAbstract
This paper follows a modeling of a cache subsystem for the RISC-V processor. The model was written in VHDL language and is targeted at soft-core applications on FPGA devices. The model is composed of two levels of cache hierarchy: the first level is directly mapped and split, while the second level is N-way set associative and unified. The model is parametrized, so the user can choose cache size as well as associativity. A simulation of a simple RISC-V processor core with a cache subsystem was done in the Vivado development tool, after which it was packaged into an IP core, implemented, and tested on the Zybo development board.
References
[1] K. Asanović, D.A. Patterson, “Instruction Sets Should Be Free: The Case For RISC-V”, EECS Dept., U.C. Berkley, CA. UCB/EECS-2014-146. Aug.6, 2014. Dostupno: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf
[2] https://riscv.org/why-risc-v/ (pristupljeno u avgustu 2020.)
[3] https://www.linuxfoundation.org/the-linux-foundation/2018/11/the-linux-foundation-and-risc-v-foundation-announce-joint-collaboration-to-enable-a-new-era-of-open-architecture/ (pristupljeno u septembru 2020.)
[4] M. V. Wilkes, “Slave Memories and Dynamic Storage Allocation”. IEEE Trans. Electron. Comput., pp. 270-271, Apr. 1965.
[5] J. C. Hoe, Predavanje, “Memory Technology and Organization” Carnegie Mellon Univ., Pittsburgh, PA, Mar. 2020. Dostupno: http://users.ece.cmu.edu/~jhoe/course/ece447/S20handouts/L14.pdf
[6] Xilinx, 7 Series FPGAs CLB User Guide (UG474) Dostupno: https://www.xilinx.com/support/
documentation/user_guides/ug474_7Series_CLB.pdf
[7] Xilinx, Zynq-7000 SoC Data Sheet: Overview (DS190), 2018. Dostupno: https://www.xilinx.com/
support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf
[8] Xilinx, 7 Series FPGAs Memory Resources User Guide (UG473), 2018. Dostupno:
https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
[9] L. Belady, “A Study of Replacement Algorithms for a Virtual-Storage Computer”. IBM Syst. J., no. 5, pp.78-101, 1966.
[10] O. Mutlu, Predavanje, “Caches”. Carnegie Mellon Univ., Pittsburgh, PA, Feb. 2015. Dostupno: https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=onur-447-spring15-lecture18-caches-afterlecture.pdf
[11] J. Bell, D. Casasent, C.G. Bell, “An Investigation of Alternative Cache Organizations”. IEEE Trans. Comput., pp. 346-351, Apr. 1974.
[12] J. Hennessy, D. Patterson, Computer Architecture : A Quantitative Approach, 6th ed., San Francisco, CA: Morgan Kaufmann Publishers Inc., 2017, pp 377-388.
[2] https://riscv.org/why-risc-v/ (pristupljeno u avgustu 2020.)
[3] https://www.linuxfoundation.org/the-linux-foundation/2018/11/the-linux-foundation-and-risc-v-foundation-announce-joint-collaboration-to-enable-a-new-era-of-open-architecture/ (pristupljeno u septembru 2020.)
[4] M. V. Wilkes, “Slave Memories and Dynamic Storage Allocation”. IEEE Trans. Electron. Comput., pp. 270-271, Apr. 1965.
[5] J. C. Hoe, Predavanje, “Memory Technology and Organization” Carnegie Mellon Univ., Pittsburgh, PA, Mar. 2020. Dostupno: http://users.ece.cmu.edu/~jhoe/course/ece447/S20handouts/L14.pdf
[6] Xilinx, 7 Series FPGAs CLB User Guide (UG474) Dostupno: https://www.xilinx.com/support/
documentation/user_guides/ug474_7Series_CLB.pdf
[7] Xilinx, Zynq-7000 SoC Data Sheet: Overview (DS190), 2018. Dostupno: https://www.xilinx.com/
support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf
[8] Xilinx, 7 Series FPGAs Memory Resources User Guide (UG473), 2018. Dostupno:
https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
[9] L. Belady, “A Study of Replacement Algorithms for a Virtual-Storage Computer”. IBM Syst. J., no. 5, pp.78-101, 1966.
[10] O. Mutlu, Predavanje, “Caches”. Carnegie Mellon Univ., Pittsburgh, PA, Feb. 2015. Dostupno: https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=onur-447-spring15-lecture18-caches-afterlecture.pdf
[11] J. Bell, D. Casasent, C.G. Bell, “An Investigation of Alternative Cache Organizations”. IEEE Trans. Comput., pp. 346-351, Apr. 1974.
[12] J. Hennessy, D. Patterson, Computer Architecture : A Quantitative Approach, 6th ed., San Francisco, CA: Morgan Kaufmann Publishers Inc., 2017, pp 377-388.
Downloads
Published
2020-11-05
Issue
Section
Electrotechnical and Computer Engineering
