Implementation of a vector processor based on a RISC-V instruction set
DOI:
https://doi.org/10.24867/10BE45KovacevicKeywords:
RISC-V, vector processor, FPGA, ZyboAbstract
This paper presents a 32-bit vector processor based on the RISC-V instruction set. The system is implemented using VHDL hardware description language for soft-core applications on FPGA platforms. The processor is split into two parts, the scalar core, that implements the RISC-V integer instruction set, and the vector core that implements the RISC-V vector instruction set. The number of vector lanes inside the vector core is parametrized, so the user can make area-versus-performance trade-offs. The system was tested on a Zybo development board, using the Vivado tool to program it, and analyze resource utilization and performance.
References
[1] J. L. Hennessy and D. A. Patterson, „Computer Architecture - A Quantitative Approach, Sixth Edition“, Morgan Kaufmann, 2017
[2] Đ. Mišeljić i N. Kovačević, Napredni mikroprocesorski sistemi, Upoznavanje sa RISC-V procesorom, 2019.
[3] A. Waterman, K. Asanović, „The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2“, CS Division, EECS Department, University of California, Berkeley, 2017.
[4] „Working draft of the proposed RISC – V „V“ vector extension“, https://github.com/riscv/riscv-v-spec (pristupljeno u septembru 2020).
[5] C. Kozyrakis and David Patterson, „Overcoming the Limitations of Conventional Vector Processors“, Proceedings of the International Symposium on Computer Architecture, 2003.
[6] Zybo reference manual, https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual (pristupljeno u septembru 2020.)
[7] https://www.xilinx.com/, (pristupljeno u septembru 2020.)
[2] Đ. Mišeljić i N. Kovačević, Napredni mikroprocesorski sistemi, Upoznavanje sa RISC-V procesorom, 2019.
[3] A. Waterman, K. Asanović, „The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2“, CS Division, EECS Department, University of California, Berkeley, 2017.
[4] „Working draft of the proposed RISC – V „V“ vector extension“, https://github.com/riscv/riscv-v-spec (pristupljeno u septembru 2020).
[5] C. Kozyrakis and David Patterson, „Overcoming the Limitations of Conventional Vector Processors“, Proceedings of the International Symposium on Computer Architecture, 2003.
[6] Zybo reference manual, https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual (pristupljeno u septembru 2020.)
[7] https://www.xilinx.com/, (pristupljeno u septembru 2020.)
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Published
2020-11-05
Issue
Section
Electrotechnical and Computer Engineering
