Simulation of TT Traffic and Performance Analysis of a Node Based on a Specific FPGA Platform in the Ethernet Network

Abstract

This paper describes the characteristics of Time-Triggered (TT) Ethernet traffic, which is used for communication between one master and several slave controllers in the network. The slave's access to the network is provided through an interface device, which filters received packets and delivers them to the slave controller. The slave controller represents an embedded Field-programmable gate array (FPGA) platform with a provided Serial Peripheral Interface (SPI) - TT module for communication with the interface controller. The paper includes an analysis of the execution of the most demanding parts of the code, as well as the impact of Best-Effort (BE) traffic on the transmission of TT messages.