IMPLEMENTATION OF CACHE COHERENCE PROTOCOL
DOI:
https://doi.org/10.24867/25BE27JankovicKeywords:
Multiprocessor Systems, Cache coherence, MESI, FPGAAbstract
This paper presents the implementation of the MESI protocol for cache coherence, as well as the rest of the multiprocessor system composed of RISC-V processors and two levels of cache memory. Behavioral simulation was used to test the behavior of the system in a situation where modified block is evicted from the second level cache.
References
[1] W. Stallings, “Computer Organization and Architecture: Designing for Performance”, 9th ed. Boston, MA: Pearson, 2013.
[2] D. Culler, J. P. Singh, and A. Gupta, “Parallel Computer Architecture: A Hardware/Software Approach”, San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 1998.
[3] T. Suh, “Integration and evaluation of cache coherence protocols for multiprocessor socs”, 2006.
[4] V. Nagarajan, D. J. Sorin, M. D. Hill, and D. A. Wood, “ A Primer on Memory Consistency and Cache Coherence”, 2nd ed. Morgan & Claypool Publishers, 2020
[5] R. H. Katz et al., “Implementing a cache consistency protocol”, ACM SIGARCH Computer Architecture News, vol. 13, no. 3, pp. 276-283, 1985.
[2] D. Culler, J. P. Singh, and A. Gupta, “Parallel Computer Architecture: A Hardware/Software Approach”, San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 1998.
[3] T. Suh, “Integration and evaluation of cache coherence protocols for multiprocessor socs”, 2006.
[4] V. Nagarajan, D. J. Sorin, M. D. Hill, and D. A. Wood, “ A Primer on Memory Consistency and Cache Coherence”, 2nd ed. Morgan & Claypool Publishers, 2020
[5] R. H. Katz et al., “Implementing a cache consistency protocol”, ACM SIGARCH Computer Architecture News, vol. 13, no. 3, pp. 276-283, 1985.
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Published
2023-12-06
Issue
Section
Electrotechnical and Computer Engineering
