DESIGN VERIFICATION ENVIRONMENT FOR APB2SPI BASED ON UVM METHODOLOGY
DOI:
https://doi.org/10.24867/01BE10LasuKeywords:
Functional verification, APB2SPI, UVM, coverageAbstract
The task of master thesis is developing verification environment for the module which is APB2SPI, based on UVM methodology and SystemVerilog programming language is used. To make documents which are verification plan and verification architecture, developing UVCs and developing tests which will check the features of design.
References
[1] Sharon Rosenberg, Kathleen A Meade; A Practical Guide to Adopting the Universal Verification Methodology (UVM); Cadence Design Systems, Inc; San Jose, USA; 2010;
[2] Chris Spear, Greg Tumbush; SystemVerilog for Verification: A Guide to Learning the Testbench Language Features; Third Edition; Springer; New York, USA; 2012;
[3] http://www.elektronika.ftn.uns.ac.rs; Sajt katedra za elektroniku; Novi Sad; Predmet: Funkcionalna verifikacija hardvera; 06.09.2018;
[2] Chris Spear, Greg Tumbush; SystemVerilog for Verification: A Guide to Learning the Testbench Language Features; Third Edition; Springer; New York, USA; 2012;
[3] http://www.elektronika.ftn.uns.ac.rs; Sajt katedra za elektroniku; Novi Sad; Predmet: Funkcionalna verifikacija hardvera; 06.09.2018;
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Published
2018-12-19
Issue
Section
Electrotechnical and Computer Engineering
