DEVELOPING UNIVERSAL VERIFICATION COMPONENT FOR APB PROTOCOL USING UVM METODOLOGY
DOI:
https://doi.org/10.24867/15BE11MihajlovicKeywords:
UVM, SystemVerilog, APB protocol, UVC, functional verificationAbstract
The task of this paper is developing the verification component for APB protocol using UVM metodology. Programming language is SystemVerilog. The paper contains inroduction into SystemVerilog and UVM. Also, results of test scenarios and functional coverage are presented.
References
[1] www.verificationacademy.com
[2] https://www.elektronika.ftn.uns.ac.rs/funkcionalna-verifikacija-hardvera/
[3] www.doulos.com
[4] Universal Verification Methodology (UVM) 1.1 User’s Guide
[5] Universal Verification Methodology (UVM) 1.1 Class Reference
[6] SystemVerilog 3.1a Language Reference Manual
[7] AMBA APB Protocol Version 2.0 Specification
[2] https://www.elektronika.ftn.uns.ac.rs/funkcionalna-verifikacija-hardvera/
[3] www.doulos.com
[4] Universal Verification Methodology (UVM) 1.1 User’s Guide
[5] Universal Verification Methodology (UVM) 1.1 Class Reference
[6] SystemVerilog 3.1a Language Reference Manual
[7] AMBA APB Protocol Version 2.0 Specification
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Published
2021-11-07
Issue
Section
Electrotechnical and Computer Engineering
