Proceeding of the Faculty of technical Sciences, Novi Sad

Electrotechnical and Computer Engineering

Vol. 36 No. 11 (2021): Proceedings of the Faculty of Technical Sciences

DEVELOPING UNIVERSAL VERIFICATION COMPONENT FOR APB PROTOCOL USING UVM METODOLOGY

  • Jovana Mihajlović
DOI:
https://doi.org/10.24867/15BE11Mihajlovic
Submitted
November 7, 2021
Published
2021-11-07

Abstract

The task of this paper is developing the verification component for APB protocol using UVM metodology. Programming language is SystemVerilog. The paper contains inroduction into SystemVerilog and UVM. Also, results of test scenarios and functional coverage are presented.

References

[1] www.verificationacademy.com
[2] https://www.elektronika.ftn.uns.ac.rs/funkcionalna-verifikacija-hardvera/
[3] www.doulos.com
[4] Universal Verification Methodology (UVM) 1.1 User’s Guide
[5] Universal Verification Methodology (UVM) 1.1 Class Reference
[6] SystemVerilog 3.1a Language Reference Manual
[7] AMBA APB Protocol Version 2.0 Specification