DESIGN OF CMOS CLOCKED COMPARATORS
DOI:
https://doi.org/10.24867/20BE01VargaKeywords:
Comparators, delay, CMOS technology, design of analog integrated circuits.Abstract
With the help of three commonly used topologies, this paper describes the design of clocked comparators. Most important parameters that define the quality of circuit, are presented. The post-layout simulation results are compared to other relevant papers.
References
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[2] B. Goll, H. Zimmermann, Comparators in Nanometer CMOS Technology, Austria, 2015.
[3] G. M. Yin, F. Op’t Eynde, and W. Sansen, A High-speed CMOS Comparator with 8-b Resolution, IEEE Journal of Solid-State Circuits. VOL. 27 , no. 2, 1992.
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[7] B. S. Patro, S. Biswas, I. Roy, B. Vandana , 1 GHz High Sensitivity Differential Current Comparator for High Speed ADC, Journal of Digital Integrated Circuits in Electrical Devices, vol. 2, no. 1, 2017.
[8] Khorami and M. Sharifkhani, A Low-Power High-Speed Comparator for Precise Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, pp. 2038–2049, 2018.
[9] N. Ghaziani, S. Radfar, Y. Bastan, P. Amiri and M. H. Maghami, A Low-Power Low-Voltage Dynamic Comparator in 180nm CMOS Technology, 2020 28th Iranian Conference on Electrical Engineering (ICEE), 2020.
[2] B. Goll, H. Zimmermann, Comparators in Nanometer CMOS Technology, Austria, 2015.
[3] G. M. Yin, F. Op’t Eynde, and W. Sansen, A High-speed CMOS Comparator with 8-b Resolution, IEEE Journal of Solid-State Circuits. VOL. 27 , no. 2, 1992.
[4] Behzad Razavi, The StrongARM Latch, IEEE Journal of Solid-State Circuits, 25 June 2015.
[5] S. Bindra, C. E. Lokin, A. Annema, B. Nauta, A 30fJ/comparison Dynamic Bias comparator, Integrated Circuit Design, 2017.
[6] A. Sathishkumar, S. Saravanan, Analysis and Design of Low Power High Speed Dynamic Latch Comparator using CMOS Process, International Journal of Scientific & Engineering Research, vol. 5, pp. 2229-5518, May 2014.
[7] B. S. Patro, S. Biswas, I. Roy, B. Vandana , 1 GHz High Sensitivity Differential Current Comparator for High Speed ADC, Journal of Digital Integrated Circuits in Electrical Devices, vol. 2, no. 1, 2017.
[8] Khorami and M. Sharifkhani, A Low-Power High-Speed Comparator for Precise Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, pp. 2038–2049, 2018.
[9] N. Ghaziani, S. Radfar, Y. Bastan, P. Amiri and M. H. Maghami, A Low-Power Low-Voltage Dynamic Comparator in 180nm CMOS Technology, 2020 28th Iranian Conference on Electrical Engineering (ICEE), 2020.
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Published
2022-11-02
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Section
Electrotechnical and Computer Engineering
