IMPLEMENTACIJA I VERIFIKACIJA SISTEMA ZA PROCESIRANJE PAKETA PRIMENOM FORMALNIH METODA
DOI:
https://doi.org/10.24867/28BE21DjokovicKeywords:
packet processing, formal verification, FPV, FSV, Hamming code, fault toleranceAbstract
The paper presents the implementation of the packet processing system, which includes the construction
of packets based on input data and configuration, and the parsing of incoming packets in order to determine the existence of errors during transmission. The system was verified using the FPV formal technique (Formal property verification), while the fault tolerance was tested using the FSV formal technique (Formal Safety Verification).
References
[1] E. Seligman, E. T. Schubert и K. M. V. A. Kiran, Formal verification: An essential toolkit for modern VLSI Design, Elsevier/Morgan Kaufmann, 2015.
[2] N. Raut, „tutorialspoint,“ [На мрежи]. Available: https://www.tutorialspoint.com/hamming-code-for-single-error-correction-double-error-detection. [Последњи приступ 22 1 2024].
[3] „LogiCORE IP AXI Interconnect,“ [На мрежи]. Available: https://www.xilinx.com/support.
[4] „JasperGold Functional Safety Verification,“ Cadence, [На мрежи]. Available: https://support.cadence.com.
[2] N. Raut, „tutorialspoint,“ [На мрежи]. Available: https://www.tutorialspoint.com/hamming-code-for-single-error-correction-double-error-detection. [Последњи приступ 22 1 2024].
[3] „LogiCORE IP AXI Interconnect,“ [На мрежи]. Available: https://www.xilinx.com/support.
[4] „JasperGold Functional Safety Verification,“ Cadence, [На мрежи]. Available: https://support.cadence.com.
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Published
2024-09-04
Issue
Section
Electrotechnical and Computer Engineering
