SOLVING THE PROBLEM OF AUTOMATING VHDL ASSIGNMENT REVIEW THROUGH THE INTEGRATION OF SYSTEM VERILOG AND PYTHON TOOLS

Authors

  • Миленко Максић Autor

DOI:

https://doi.org/10.24867/33BE14Maksic

Keywords:

automated evaluation, SystemVerilog, digital design

Abstract

This paper presents a system for automated evaluation of student assignments written in VHDL, integrating SystemVerilog verification tools with Python scripts for result analysis. The goal is to accelerate and standardize the grading process, especially in large academic groups. SystemVerilog is used to define assertion and test scenarios, while Python automates simulation execution, log parsing, and score report generation. The system was applied to a dataset of 223 student submissions, and the results were compared with manual grading. The analysis shows that automated evaluation can significantly reduce grading time and improve objectivity, but also highlights challenges in fairly assessing partially correct solutions – an important consideration in educational environments.

References

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Published

2026-01-30

Issue

Section

Electrotechnical and Computer Engineering